Computer architecture revisited

ISA (Instruction Set Architecture): CISC (Complex Instruction Set Computer) vs RISC (Reduced Instruction Set Computer)

CISC – larger, more feature-rich instruction set (more operations, addressing modes, etc.). slower clock speeds. fewer general purpose registers. Examples: x86 variants.

RISC – smaller, simpler instruction set. faster clock speeds. more general purpose registers. Examples: ARM, MIPS, PowerPC, AVR, etc.

EPIC – permits microprocessors to execute software instructions in parallel by using the compiler, rather than complex on-die circuitry, to control parallel instruction execution.

The performance – how fast a processor?

Q&A

Q: Why RISC CPUs need faster clock speed?

A: RISC CPUs generally run at faster clock speeds than CISC because max clock period is dictated by the slowest step of the pipeline (more complex instructions are slower).

Q: Why RISC need more RAM?

A: Because of small number of instructions, RISC need more lines of code, so more RAM is needed to store the assembly level instructions.

Q: Why RISC consumes less power than CISC?

A: In simple (computer Architecture 101)

• RISC has few, simple instructions. The hardware is highly optimized for each one.
• CISC has lots of instructions. That needs a more complex decode logic (gates, power, area), and those instructions need a lot of complex logic to implement them (gates, power, area).

Register memory vs Load/store architecture

From Wikipedia, the free encyclopedia

In computer engineering a register memory architecture allows operations to be performed on (or from) memory, as well as registers.^[1] If the architecture allows all operands to be in memory or in registers, or in combinations, it is called a “register plus memory” architecture.^[1]

In a register memory approach one of the operands for ADD operation may be in memory, while the other is in a register. This differs from a load/store architecture (used by RISC designs such as MIPS) in which both operands for an ADD operation must be in registers before the ADD.^[1]

Examples of register memory architecture are IBM System/360, its successors, and Intel x86.^[1] Examples of register plus memory architecture are VAX and the Motorola 68000 family.^[1]

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From Wikipedia, the free encyclopedia

In computer engineering, a load/store architecture divides instructions into 2 categories: memory access (load and store between memory and registers), and ALUoperations (which only occur between registers).^[1]:9-12

RISC systems such as PowerPC, SPARC, RISC-V, ARM or MIPS use the load/store architecture.^[1]:9-12

For instance, in a load/store approach both operands and destination for an ADD operation must be in registers. This differs from a register memory architecture (used by CISC designs such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.^[1]:9-12

The earliest example of a load/store architecture was the CDC 6600.^[1]:54-56 Almost all vector processors (including many GPUs^[2]) use the load/store approach.^[3]

Refs:

• https://en.wikipedia.org/wiki/Comparison_of_instruction_set_architectures
• https://www.microcontrollertips.com/risc-vs-cisc-architectures-one-better/
• https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/
• https://sites.google.com/site/jdsarodeprogramming/computer-architecture/cisc-vs-risc?authuser=0